Differences

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--- en:hw:connection-of-edge-do-hidden [2024/10/29 12:49] – created avsetula
+++ en:hw:connection-of-edge-do-hidden [2025/07/23 08:30] (current) – typo ofojt
@@ Line 1: / Line 1: @@
-Digital outputs (semiconductive, connected as open collectors) are wired to **DOx** or **DOy.x** terminals on the connector. Each connector also features a common **DOGND** terminal for connecting negative pole of a DC power source. Digital outputs do not possess their own power source and serve only for switching the power source's negative pole from DOGND terminal to the individual DOx outputs where loads can be connected. Switching of each output is indicated by LED with the corresponding label matching the output's marking. The FBD terminal can be used with some loads - see below for more info.
+/*
+Each digital output (solid state MOSFET relay) is available on separate **DOx** terminals on the terminal block. When wiring, the polarity does not matter, but it must be respected that the load is switched to ground. Digital outputs do not possess their own power source. Switching of each output is indicated by LED with the label and number corresponding to the output.
+*/
-<WRAP center round info 95%>
+Each digital output (solid state MOSFET relay) is wired to its own **DOx** connector. To switch inductive /* or capacitive */ loads, it is necessary to connected adequate protection, e.g. snubber, otherwise there is a risk of possible damage to the device's digital outputs. Both terminals can be wired with both positive and negative polarity. Switching of each output is indicated by LED with the label and number corresponding to the output.
+<WRAP group center round box 95%>
+{{ :files:img_warning-line_b.png?nolink |}}
+<WRAP half column 13%>
+{{ :en:hw:08_safety-instructions_pseudo-ISO-7010-info.png?nolink |(!)}}
+</WRAP>
+<WRAP half column 83%>
 **Note:** \\
-Digital outputs can be configured to [[#pwm|PWM mode]] (pulse width modulation) using a suitable SW (Mervis, EVOK or by directly editing the registers)
+Digital outputs do not possess their own power source (meaning they are dry contacts) and serve only to switch **A** and **B** terminals together where the load can be connected. This means that if 28 V are supplied to one of the terminals and the digital output is on, then same voltage would appear on the other terminal.
+</WRAP>
+</WRAP>
+<WRAP group center round box 95%>
+{{ :files:img_warning-line_b.png?nolink |}}
+<WRAP half column 13%>
+{{ :en:hw:08_safety-instructions_pseudo-ISO-7010-info.png?nolink |(!)}}
+</WRAP>
+<WRAP half column 83%>
+**Note:** \\
+Digital outputs can be configured to [[#pwm|PWM mode]] (pulse width modulation) using a suitable SW (Mervis, EVOK or by directly editing the Modbus registers).
+</WRAP>
 </WRAP>
 ====== Connection ======
-The following picture describes the basic connection of digital output:
+The following pictures describe the basic connection of digital output:
-{{ :en:hw:002_connection_of_io.png?direct&200 |}}
+<WRAP group center round box 95%>
+{{ :files:img_warning-line_b.png?nolink |}}
+<WRAP half column 13%>
+{{ :en:hw:09_safety-instructions_pseudo-ISO-7010-attention.png?nolink |(!)}}
+</WRAP>
+<WRAP half column 83%>
+**Attention:** \\
+To switch some loads it is necessary to add adequate protection elements, e.g. snubber!
+</WRAP>
+</WRAP>
-<html><div class="directTag" id="fbd"></div></html>
+<WRAP group>
-We recommend using the flyback diode available on the **FBD** terminal to prevent unwanted spikes when using certain loads (such as external relays) connected to digital outputs. The following picture depicts the connection of a contactor to digital output using the integrated FBD diode.
+<WRAP half column>
+;#;
-{{ :en:hw:003_connection_of_io.png?direct&300 |}}
+//SINK//
+;#;
-<WRAP center round important 95%>
+{{ :en:hw:002_connection_of_edge2_io.png?direct&200 |}}
-**Caution!** \\
+</WRAP>
-The integrated diode is designed only for connecting devices within a single group of DO. Using the diode for other connections can cause irreversible damage to the device.
+<WRAP half column>
+;#;
+//SOURCE//
+;#;
+{{ :en:hw:0021_connection_of_edge2_io.png?direct&200 |}}
+</WRAP>
 </WRAP>